Hi Sergey,
> Subject: Re: [PATCH net-next v4] ravb: Add RZ/G2L MII interface support
>
> On 9/14/22 8:53 PM, Biju Das wrote:
>
> > EMAC IP found on RZ/G2L Gb ethernet supports MII interface.
> > This patch adds support for selecting MII interface mode.
> >
> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > ---
> > v3->v4:
> > * Dropped CXR35_HALFCYC_CLKSW1000 macro
>
> It's not macro...
>
> > * Added CXR35_HALFCYC_CLKSW, CXR35_SEL_XMII and CXR35_SEL_XMII_RGMII
> > macros.
>
> Neither are these...
>
> > v2->v3:
> > * Documented CXR35_HALFCYC_CLKSW1000 and CXR35_SEL_XMII_MII macros.
> > v1->v2:
> > * Fixed spaces->Tab around CXR35 description.
> > ---
> > drivers/net/ethernet/renesas/ravb.h | 8 ++++++++
> > drivers/net/ethernet/renesas/ravb_main.c | 8 +++++++-
> > 2 files changed, 15 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/net/ethernet/renesas/ravb.h
> > b/drivers/net/ethernet/renesas/ravb.h
> > index b980bce763d3..b445da0fa578 100644
> > --- a/drivers/net/ethernet/renesas/ravb.h
> > +++ b/drivers/net/ethernet/renesas/ravb.h
> [...]
> > @@ -965,6 +966,13 @@ enum CXR31_BIT {
> > CXR31_SEL_LINK1 = 0x00000008,
> > };
> >
> > +enum CXR35_BIT {
> > + CXR35_HALFCYC_CLKSW = 0xffff0000,
>
> Should come last...
Ok, will do. If everyone ok with it.
>
> [...]
> > diff --git a/drivers/net/ethernet/renesas/ravb_main.c
> > b/drivers/net/ethernet/renesas/ravb_main.c
> > index b357ac4c56c5..421c8ff1ce1f 100644
> > --- a/drivers/net/ethernet/renesas/ravb_main.c
> > +++ b/drivers/net/ethernet/renesas/ravb_main.c
> > @@ -540,7 +540,13 @@ static void ravb_emac_init_gbeth(struct net_device
> *ndev)
> > /* E-MAC interrupt enable register */
> > ravb_write(ndev, ECSIPR_ICDIP, ECSIPR);
> >
> > - ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1,
> CXR31_SEL_LINK0);
> > + if (priv->phy_interface == PHY_INTERFACE_MODE_MII) {
> > + ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1,
> 0);
> > + ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_MII, CXR35);
> > + } else {
> > + ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1,
> > + CXR31_SEL_LINK0);
>
> Hm... According to the RZ/G2LC manual, we still have to set
> CSR35.HALFCYC_CLKSW to
> 1000 even for RGMII... We probably need something more sophisticated here,
> like a flag in the *struct* ravb_hw_info...
Strictly not required, as it is based on In-band Status.
It is one of to do's in my backlog to add
XMII selection for PHY which does not support In-band Status.
Cheers,
Biju
