Enable the I2C0 bus on the White Hawk CPU board, and describe the I2C
EEPROMs present on the White Hawk CPU and BreakOut boards.
Based on a larger patch in the BSP by Takeshi Kihara.
Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
---
Changes compared to the BSP:
- Add missing BreakOut board EEPROM.
---
.../dts/renesas/r8a779g0-white-hawk-cpu.dtsi | 20 +++++++++++++++++++
.../boot/dts/renesas/r8a779g0-white-hawk.dts | 9 +++++++++
2 files changed, 29 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi
index ba8cc162076cd8bf..27daba944a3385db 100644
--- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi
@@ -40,6 +40,21 @@ &hscif0 {
status = "okay";
};
+&i2c0 {
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ eeprom@50 {
+ compatible = "rohm,br24g01", "atmel,24c01";
+ label = "cpu-board";
+ reg = <0x50>;
+ pagesize = <8>;
+ };
+};
+
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
@@ -49,6 +64,11 @@ hscif0_pins: hscif0 {
function = "hscif0";
};
+ i2c0_pins: i2c0 {
+ groups = "i2c0";
+ function = "i2c0";
+ };
+
scif_clk_pins: scif_clk {
groups = "scif_clk";
function = "scif_clk";
diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts
index bc0ac109b17cec30..afa807e4f7043455 100644
--- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts
+++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts
@@ -20,3 +20,12 @@ chosen {
stdout-path = "serial0:921600n8";
};
};
+
+&i2c0 {
+ eeprom@51 {
+ compatible = "rohm,br24g01", "atmel,24c01";
+ label = "breakout-board";
+ reg = <0x51>;
+ pagesize = <8>;
+ };
+};
--
2.25.1
