Hi Geert, > Subject: Re: [RFC PATCH 1/2] riscv: vendors: andes: Add support to > configure the PMA regions > > Hi Biju, > > On Thu, Sep 8, 2022 at 3:01 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > wrote: > > > Subject: Re: [RFC PATCH 1/2] riscv: vendors: andes: Add support to > > > configure the PMA regions > > > > > > On 08/09/2022 09:39, Biju Das wrote: > > > > EXTERNAL EMAIL: Do not click links or open attachments unless you > > > > know the content is safe > > > > > > > > Hi Conor, Atish, > > > > > > > > What RISC-V devices you have? > > > > > > A bunch ;) > > > > > > A __couple__ PolarFire SoC boards, HiFive Unleashed, D1 Nezha, > > > Canaan > > > k210 MAIX something & the VisionFive. > > > > If standard DMA api works without any issue means, on these platforms > > IO Coherence port is enabled in the hardware. So all peripherals > > involving DMA work as expected. > > > > > > Ours is RISC-V uniprocessor without IO Coherence Port. > > > > > > What does "IO Coherence Port" mean? Zicbo*? > > > > The HW will provide coherency between CPU and peripheral. > > > > If Zibco* is uniprocessor, then highly it may not have IO coherence > > Port enabled in their design. > > Zicbo* is a set of extensions for the instructions. > These cannot be retrofitted to existing silicon, but perhaps they can be > trapped and emulated? Thanks for clarifying this. I just gone through RISC-V CMOs. https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.1.pdf Cheers, Biju
