Hello Sergei-san,
> From: Sergei Shtylyov, Sent: Monday, September 5, 2022 5:40 PM
>
> Hello!
>
> On 9/5/22 10:12 AM, Yoshihiro Shimoda wrote:
>
> > Since reading value of PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL was
> > 0x00000000 on one of SoCs (R-Car S4-8), it cannot find the eDMA.
> > So, directly read the eDMA register if edma.red_base is not zero.
>
> s/red/reg/?
Thank you for your review! I'll fix it.
Best regards,
Yoshihiro Shimoda
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
> > ---
> > drivers/pci/controller/dwc/pcie-designware.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> > index 72f9620a374d..08f91a6bbe4b 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > @@ -844,8 +844,7 @@ static int dw_pcie_edma_find_chip(struct dw_pcie *pci)
> > {
> > u32 val;
> >
> > - val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL);
> > - if (val == 0xFFFFFFFF && pci->edma.reg_base) {
> > + if (pci->edma.reg_base) {
> > pci->edma.mf = EDMA_MF_EDMA_UNROLL;
> >
> > val = dw_pcie_readl_dma(pci, PCIE_DMA_CTRL);
> [...]
>
> MBR, Sergey
