On Tue, Aug 2, 2022 at 12:15 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> As per the RZ/G2UL Hardware User's Manual (Rev.1.00 Apr, 2022),
> the interrupt type of SCI{Rx,TX} is edge triggered.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Fixes: cf40c9689e5109bf ("arm64: dts: renesas: Add initial DTSI for
RZ/G2UL SoC")
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-devel for v6.1.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
