Hi Biju, On Wed, Jul 27, 2022 at 10:27 AM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote: > > Hi Lad, Prabhakar, > > > Subject: Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding > > documentation for Renesas RZ/Five SoC and SMARC EVK > > > > Hi Krzysztof, > > > > Thank you for the review. > > > > On Wed, Jul 27, 2022 at 9:54 AM Krzysztof Kozlowski > > <krzysztof.kozlowski@xxxxxxxxxx> wrote: > > > > > > On 26/07/2022 20:06, Lad Prabhakar wrote: > > > > Document Renesas RZ/Five (R9A07G043) SoC and SMARC EVK based on this > > SoC. > > > > > > > > Signed-off-by: Lad Prabhakar > > > > <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > > > --- > > > > .../devicetree/bindings/riscv/renesas.yaml | 49 > > +++++++++++++++++++ > > > > 1 file changed, 49 insertions(+) > > > > create mode 100644 > > > > Documentation/devicetree/bindings/riscv/renesas.yaml > > > > > > > > diff --git a/Documentation/devicetree/bindings/riscv/renesas.yaml > > > > b/Documentation/devicetree/bindings/riscv/renesas.yaml > > > > new file mode 100644 > > > > index 000000000000..f72f8aea6a82 > > > > --- /dev/null > > > > +++ b/Documentation/devicetree/bindings/riscv/renesas.yaml > > > > @@ -0,0 +1,49 @@ > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 > > > > +--- > > > > +$id: > > > > > + > > > > +title: Renesas RZ/Five Platform Device Tree Bindings > > > > + > > > > +maintainers: > > > > + - Geert Uytterhoeven <geert+renesas@xxxxxxxxx> > > > > + - Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > > > + > > > > +# We want to ignore this schema if the board is SMARC EVK based on > > > > +ARM64 arch > > > > +select: > > > > + not: > > > > + properties: > > > > + compatible: > > > > + contains: > > > > + items: > > > > > > I think you should rather ignore the RiscV SoCs, not specific board. > > > > > You mean to ignore ARM/64 SoCs? > > > > Agreed just the below enum, should do the trick. > > > > - enum: > > - renesas,r9a07g043u11 > > - renesas,r9a07g043u12 > > - renesas,r9a07g044c1 > > - renesas,r9a07g044c2 > > - renesas,r9a07g044l1 > > - renesas,r9a07g044l2 > > - renesas,r9a07g054l1 > > - renesas,r9a07g054l2 > > Why do we need to add renesas,r9a07g044 and renesas,r9a07g054 > in riscv file? These are arm64 only SoC's. > The above needs to be added to avoid dtbs_check/dt_binding_check errors. The above hunk ignores the RISC-V schema if it's an ARM64 SoC. Cheers, Prabhakar > Cheers, > Biju > > > > > > > > > + - const: renesas,smarc-evk > > > > + - enum: > > > > + - renesas,r9a07g043u11 > > > > + - renesas,r9a07g043u12 > > > > + - renesas,r9a07g044c1 > > > > + - renesas,r9a07g044c2 > > > > + - renesas,r9a07g044l1 > > > > + - renesas,r9a07g044l2 > > > > + - renesas,r9a07g054l1 > > > > + - renesas,r9a07g054l2 > > > > + - enum: > > > > + - renesas,r9a07g043 > > > > + - renesas,r9a07g044 > > > > + - renesas,r9a07g054 > > > > > > Did you actually test that it works and properly matches? > > > > > Yes I have run the dtbs_check and dt_binding _check for ARM64 and RISC- > > V. Do you see any cases where it can fail? > > > > Cheers, > > Prabhakar
