On 26/07/2022 20:06, Lad Prabhakar wrote: > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP > Single). > > Below is the list of IP blocks added in the initial SoC DTSI which can be > used to boot via initramfs on RZ/Five SMARC EVK: > - AX45MP CPU > - CPG > - PINCTRL > - PLIC > - SCIF0 > - SYSC > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > --- > arch/riscv/boot/dts/Makefile | 1 + > arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++ > 2 files changed, 122 insertions(+) > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi > > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile > index ff174996cdfd..b0ff5fbabb0c 100644 > --- a/arch/riscv/boot/dts/Makefile > +++ b/arch/riscv/boot/dts/Makefile > @@ -3,5 +3,6 @@ subdir-y += sifive > subdir-y += starfive > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan > subdir-y += microchip > +subdir-y += renesas What are you building there? There is no DTS. Best regards, Krzysztof
