On Tue, Jul 19, 2022 at 04:00:00PM +0100, Biju Das wrote:
> RSPI IP on RZ/{A, G2L} SoC's has the same signal for both interrupt and
> DMA transfer request. Setting DMARS register for DMA transfer
> makes the signal to work as a DMA transfer request signal and
> subsequent interrupt requests to the interrupt controller
> are masked.
Acked-by: Mark Brown <broonie@xxxxxxxxxx>
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