On 13/07/2022 15:55, Biju Das wrote: > Add device tree bindings for the RZ/G2L Port Output Enable for GPT (POEG). > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > --- > REF->v1: > * Modelled as pincontrol as most of its configuration is intended to be > static. > * Updated reg size in example. > --- > .../bindings/pinctrl/renesas,rzg2l-poeg.yaml | 65 +++++++++++++++++++ > 1 file changed, 65 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml > > diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml > new file mode 100644 > index 000000000000..7607dd87fa68 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml > @@ -0,0 +1,65 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-poeg.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas RZ/G2L Port Output Enable for GPT (POEG) > + > +maintainers: > + - Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > + > +description: | > + The output pins of the general PWM timer (GPT) can be disabled by using > + the port output enabling function for the GPT (POEG). Specifically, > + either of the following ways can be used. > + * Input level detection of the GTETRGA to GTETRGD pins. > + * Output-disable request from the GPT. Shouldn't this all be part of GPT? Is this a real separate device in the SoC? > + * Register settings. This is confusing... so you can use POEG to mess up registers of GPT independently, so GPT does not know it? > + > +properties: > + compatible: > + items: > + - enum: > + - renesas,r9a07g044-poeg # RZ/G2{L,LC} > + - renesas,r9a07g054-poeg # RZ/V2L > + - const: renesas,rzg2l-poeg > + Best regards, Krzysztof
