The scif0 nodes were accidentally inserted after the scif3 nodes,
breaking alphabetical sort order.
Fixes: 1614c8624a48b9c9 ("arm64: dts: renesas: spider-cpu: Enable SCIF0 on second connector")
Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
---
To be queued in renesas-devel for v5.20.
.../boot/dts/renesas/r8a779f0-spider-cpu.dtsi | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
index 7fa225dafa6e5749..2cc365a720c19fc5 100644
--- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
@@ -55,16 +55,16 @@ i2c4_pins: i2c4 {
function = "i2c4";
};
- scif3_pins: scif3 {
- groups = "scif3_data", "scif3_ctrl";
- function = "scif3";
- };
-
scif0_pins: scif0 {
groups = "scif0_data", "scif0_ctrl";
function = "scif0";
};
+ scif3_pins: scif3 {
+ groups = "scif3_data", "scif3_ctrl";
+ function = "scif3";
+ };
+
scif_clk_pins: scif_clk {
groups = "scif_clk";
function = "scif_clk";
@@ -76,16 +76,16 @@ &rwdt {
status = "okay";
};
-&scif3 {
- pinctrl-0 = <&scif3_pins>;
+&scif0 {
+ pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
-&scif0 {
- pinctrl-0 = <&scif0_pins>;
+&scif3 {
+ pinctrl-0 = <&scif3_pins>;
pinctrl-names = "default";
uart-has-rtscts;
--
2.25.1
