Hi Morimoto-san,
On Fri, Jul 1, 2022 at 3:40 AM Kuninori Morimoto
<kuninori.morimoto.gx@xxxxxxxxxxx> wrote:
> From: Kuninori Morimoto <kuninori.morimoto.gx@xxxxxxxxxxx>
>
> V4H has PWM/PWM_A/PWM_B, but current PFC setting is mixed.
> This patch add missing PWM settings, and tidyup these.
>
> According to Document, GP3_14 Function4 is PWM2_A,
> but we can't select it at P1SR3[27:24].
> This patch just ignore it for now.
>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@xxxxxxxxxxx>
Thanks for your patch!
> --- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
> /* - QSPI0 ------------------------------------------------------------------ */
> @@ -2556,16 +2576,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
> SH_PFC_PIN_GROUP(pcie0_clkreq_n),
> SH_PFC_PIN_GROUP(pcie1_clkreq_n),
>
> - SH_PFC_PIN_GROUP(pwm0),
> - SH_PFC_PIN_GROUP(pwm1),
> - SH_PFC_PIN_GROUP(pwm2),
> - SH_PFC_PIN_GROUP(pwm3),
> + SH_PFC_PIN_GROUP(pwm0_a),
> + SH_PFC_PIN_GROUP(pwm1_a),
> + SH_PFC_PIN_GROUP(pwm1_b),
> + SH_PFC_PIN_GROUP(pwm2_b),
> + SH_PFC_PIN_GROUP(pwm3_a),
> + SH_PFC_PIN_GROUP(pwm3_b),
> SH_PFC_PIN_GROUP(pwm4),
> SH_PFC_PIN_GROUP(pwm5),
> SH_PFC_PIN_GROUP(pwm6),
> SH_PFC_PIN_GROUP(pwm7),
> - SH_PFC_PIN_GROUP(pwm8),
> - SH_PFC_PIN_GROUP(pwm9),
> + SH_PFC_PIN_GROUP(pwm8_a),
> + SH_PFC_PIN_GROUP(pwm9_a),
The groups for PWMs that are available on a single pin, but do have
a suffix (pwm[089]_a and pwm2_b), may need to be renamed later.
I'll add a /* suffix might be updated */ comment while applying.
>
> SH_PFC_PIN_GROUP(qspi0_ctrl),
> BUS_DATA_PIN_GROUP(qspi0_data, 2),
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-pinctrl-for-v5.20.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
