Add CAN binding documentation for Renesas RZ/N1 SoC.
The SJA1000 CAN controller on RZ/N1 SoC has some differences compared
to others like it has no clock divider register (CDR) support and it has
no HW loopback (HW doesn't see tx messages on rx), so introduced a new
compatible 'renesas,rzn1-sja1000' to handle these differences.
Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
---
v2->v3:
* Added reg-io-width is required property for renesas,rzn1-sja1000.
v1->v2:
* Updated commit description.
* Added an example for RZ/N1D SJA1000 usage
---
.../bindings/net/can/nxp,sja1000.yaml | 35 +++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/can/nxp,sja1000.yaml b/Documentation/devicetree/bindings/net/can/nxp,sja1000.yaml
index d34060226e4e..16786475eae3 100644
--- a/Documentation/devicetree/bindings/net/can/nxp,sja1000.yaml
+++ b/Documentation/devicetree/bindings/net/can/nxp,sja1000.yaml
@@ -19,6 +19,16 @@ allOf:
then:
required:
- reg-io-width
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,rzn1-sja1000
+ then:
+ required:
+ - clocks
+ - clock-names
+ - reg-io-width
properties:
compatible:
@@ -27,6 +37,12 @@ properties:
const: nxp,sja1000
- description: Technologic Systems SJA1000 CAN Controller
const: technologic,sja1000
+ - description: Renesas RZ/N1 SJA1000 CAN Controller
+ items:
+ - enum:
+ - renesas,r9a06g032-sja1000 # RZ/N1D
+ - renesas,r9a06g033-sja1000 # RZ/N1S
+ - const: renesas,rzn1-sja1000 # RZ/N1
reg:
maxItems: 1
@@ -34,6 +50,12 @@ properties:
interrupts:
maxItems: 1
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: can_clk
+
reg-io-width:
$ref: /schemas/types.yaml#/definitions/uint32
description: I/O register width (in bytes) implemented by this device
@@ -101,3 +123,16 @@ examples:
nxp,tx-output-config = <0x06>;
nxp,external-clock-frequency = <24000000>;
};
+
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/r9a06g032-sysctrl.h>
+
+ can@52104000 {
+ compatible = "renesas,r9a06g032-sja1000","renesas,rzn1-sja1000";
+ reg = <0x52104000 0x800>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sysctrl R9A06G032_HCLK_CAN0>;
+ clock-names = "can_clk";
+ };
--
2.25.1
