Hi Marc and Uwe,
> Subject: Re: [PATCH 6/6] can: sja1000: Add support for RZ/N1 SJA1000 CAN
> Controller
>
> On 02.07.2022 15:01:30, Biju Das wrote:
> > The SJA1000 CAN controller on RZ/N1 SoC has some differences compared
> > to others like it has no clock divider register (CDR) support and it
> > has no HW loopback(HW doesn't see tx messages on rx).
> >
> > This patch adds support for RZ/N1 SJA1000 CAN Controller.
> >
> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > ---
> > drivers/net/can/sja1000/sja1000_platform.c | 34
> > ++++++++++++++++++----
> > 1 file changed, 29 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/net/can/sja1000/sja1000_platform.c
> > b/drivers/net/can/sja1000/sja1000_platform.c
> > index 5f3d362e0da5..8e63af76a013 100644
> > --- a/drivers/net/can/sja1000/sja1000_platform.c
> > +++ b/drivers/net/can/sja1000/sja1000_platform.c
> [...]
> > @@ -262,6 +276,16 @@ static int sp_probe(struct platform_device *pdev)
> > priv->reg_base = addr;
> >
> > if (of) {
> > + clk = devm_clk_get_optional(&pdev->dev, "can_clk");
> > + if (IS_ERR(clk))
> > + return dev_err_probe(&pdev->dev, PTR_ERR(clk), "no CAN
> clk");
> > +
> > + if (clk) {
> > + priv->can.clock.freq = clk_get_rate(clk) / 2;
> > + if (!priv->can.clock.freq)
> > + return dev_err_probe(&pdev->dev, -EINVAL, "Zero
> CAN clk rate");
> > + }
>
> There's no clk_prepare_enable in the driver. You might go the quick and
> dirty way an enable the clock right here. IIRC there's a new convenience
> function to get and enable a clock, managed bei devm. Uwe (Cc'ed) can
> point you in the right direction.
+ clk
As per the patch history devm version for clk_prepare_enable is rejected[1], so the individual drivers implemented the same using devm_add_action_or_reset [2].
So shall I implement devm version here as well?
[1]https://lkml.iu.edu/hypermail/linux/kernel/2103.1/01556.html
[2] https://elixir.bootlin.com/linux/v5.19-rc4/source/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c#L266
Cheers,
Biju
