On 02.07.2022 15:01:26, Biju Das wrote:
> Add CAN binding documentation for Renesas RZ/N1 SoC.
>
> The SJA1000 CAN controller on RZ/N1 SoC has some differences compared
> to others like it has no clock divider register (CDR) support and it has
> no HW loopback(HW doesn't see tx messages on rx), so introduced a new
^^^
please add space.
> compatible 'renesas,rzn1-sja1000' to handle these differences.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> ---
> .../bindings/net/can/nxp,sja1000.yaml | 22 +++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/net/can/nxp,sja1000.yaml b/Documentation/devicetree/bindings/net/can/nxp,sja1000.yaml
> index 91d0f1b25d10..d0d374b979ec 100644
> --- a/Documentation/devicetree/bindings/net/can/nxp,sja1000.yaml
> +++ b/Documentation/devicetree/bindings/net/can/nxp,sja1000.yaml
> @@ -16,6 +16,12 @@ properties:
> const: nxp,sja1000
> - description: Technologic Systems SJA1000 CAN Controller
> const: technologic,sja1000
> + - description: Renesas RZ/N1 SJA1000 CAN Controller
> + items:
> + - enum:
> + - renesas,r9a06g032-sja1000 # RZ/N1D
> + - renesas,r9a06g033-sja1000 # RZ/N1S
> + - const: renesas,rzn1-sja1000 # RZ/N1
>
> reg:
> maxItems: 1
> @@ -23,6 +29,12 @@ properties:
> interrupts:
> maxItems: 1
>
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + const: can_clk
> +
> reg-io-width:
> $ref: /schemas/types.yaml#/definitions/uint32
> description: I/O register width (in bytes) implemented by this device
> @@ -91,6 +103,16 @@ allOf:
> required:
> - reg-io-width
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: renesas,rzn1-sja1000
> + then:
> + required:
> + - clocks
> + - clock-names
> +
> unevaluatedProperties: false
>
> examples:
Can you add an example, too?
Marc
--
Pengutronix e.K. | Marc Kleine-Budde |
Embedded Linux | https://www.pengutronix.de |
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