Hi Marc,
Thank you for the review.
On Wed, Jun 29, 2022 at 5:26 PM Marc Zyngier <maz@xxxxxxxxxx> wrote:
>
> On Sat, 25 Jun 2022 21:06:00 +0100,
> Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> wrote:
> >
> > Add IRQ domain to RZ/G2L pinctrl driver to handle GPIO interrupt.
> >
> > GPIO0-GPIO122 pins can be used as IRQ lines but only 32 pins can be
> > used as IRQ lines at a given time. Selection of pins as IRQ lines
> > is handled by IA55 (which is the IRQC block) which sits in between the
> > GPIO and GIC.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > ---
> > drivers/pinctrl/renesas/pinctrl-rzg2l.c | 236 ++++++++++++++++++++++++
> > 1 file changed, 236 insertions(+)
> >
>
> [...]
>
> > +static void *rzg2l_gpio_populate_parent_fwspec(struct gpio_chip *chip,
> > + unsigned int parent_hwirq,
> > + unsigned int parent_type)
> > +{
> > + struct irq_fwspec *fwspec;
> > +
> > + fwspec = kzalloc(sizeof(*fwspec), GFP_KERNEL);
> > + if (!fwspec)
> > + return NULL;
> > +
> > + fwspec->fwnode = chip->irq.parent_domain->fwnode;
> > + fwspec->param_count = 2;
> > + fwspec->param[0] = parent_hwirq;
> > + fwspec->param[1] = parent_type;
> > +
> > + return fwspec;
> > +}
>
> I jumped at this one again.
>
> Can you please pick [1] as part of your series and write this in a way
> that doesn't require extra memory allocation? It has already been
> ack'ed by Linus anyway, and we'd put an end to this thing for good.
>
Sure will update and post a v7.
Cheers,
Prabhakar
