Hi Morimoto-san,
On Tue, Jun 14, 2022 at 8:00 AM Kuninori Morimoto
<kuninori.morimoto.gx@xxxxxxxxxxx> wrote:
> From: Kuninori Morimoto <kuninori.morimoto.gx@xxxxxxxxxxx>
>
> V4H has SCIF3 and SCIF3_A, but current PFC setting is mixed.
> Exising SCIF3 settings on IP3SR1 should be SCIF3_A,
> and existing settings on scif3_xxx[] are for SCIF3.
>
> This patch add missing SCIF3 settings on IP0SR1,
> rename IP3SR1 settings to SCIF3_A,
> add missing scif3_a_xxx[].
>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@xxxxxxxxxxx>
Thanks for your patch!
> --- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
> @@ -319,11 +319,11 @@
> #define IP2SR1_31_28 F_(0, 0) FM(TCLK2) FM(MSIOF4_SS1) FM(IRQ3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
>
> /* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
> -#define IP3SR1_3_0 FM(HRX3) FM(SCK3) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> -#define IP3SR1_7_4 FM(HSCK3) FM(CTS3_N) FM(MSIOF4_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> -#define IP3SR1_11_8 FM(HRTS3_N) FM(RTS3_N) FM(MSIOF4_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> -#define IP3SR1_15_12 FM(HCTS3_N) FM(RX3) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> -#define IP3SR1_19_16 FM(HTX3) FM(TX3) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> +#define IP3SR1_3_0 FM(HRX3) FM(SCK3_A) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> +#define IP3SR1_7_4 FM(HSCK3) FM(CTS3_A_N) FM(MSIOF4_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
CTS3_N_A (everywhere)
> +#define IP3SR1_11_8 FM(HRTS3_N) FM(RTS3_A_N) FM(MSIOF4_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
RTS3_N_A (everywhere)
> +#define IP3SR1_15_12 FM(HCTS3_N) FM(RX3_A) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> +#define IP3SR1_19_16 FM(HTX3) FM(TX3_A) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
I think this part belongs in "[PATCH v3 03/21] pinctrl: renesas:
Initial R8A779G0 (V4H) PFC support", as it is a bug in that patch.
>
> /* SR2 */
> /* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
> @@ -901,23 +906,23 @@ static const u16 pinmux_data[] = {
>
> /* IP3SR1 */
> PINMUX_IPSR_GPSR(IP3SR1_3_0, HRX3),
> - PINMUX_IPSR_GPSR(IP3SR1_3_0, SCK3),
> + PINMUX_IPSR_GPSR(IP3SR1_3_0, SCK3_A),
> PINMUX_IPSR_GPSR(IP3SR1_3_0, MSIOF4_SS2),
>
> PINMUX_IPSR_GPSR(IP3SR1_7_4, HSCK3),
> - PINMUX_IPSR_GPSR(IP3SR1_7_4, CTS3_N),
> + PINMUX_IPSR_GPSR(IP3SR1_7_4, CTS3_A_N),
> PINMUX_IPSR_GPSR(IP3SR1_7_4, MSIOF4_SCK),
>
> PINMUX_IPSR_GPSR(IP3SR1_11_8, HRTS3_N),
> - PINMUX_IPSR_GPSR(IP3SR1_11_8, RTS3_N),
> + PINMUX_IPSR_GPSR(IP3SR1_11_8, RTS3_A_N),
> PINMUX_IPSR_GPSR(IP3SR1_11_8, MSIOF4_TXD),
>
> PINMUX_IPSR_GPSR(IP3SR1_15_12, HCTS3_N),
> - PINMUX_IPSR_GPSR(IP3SR1_15_12, RX3),
> + PINMUX_IPSR_GPSR(IP3SR1_15_12, RX3_A),
> PINMUX_IPSR_GPSR(IP3SR1_15_12, MSIOF4_RXD),
>
> PINMUX_IPSR_GPSR(IP3SR1_19_16, HTX3),
> - PINMUX_IPSR_GPSR(IP3SR1_19_16, TX3),
> + PINMUX_IPSR_GPSR(IP3SR1_19_16, TX3_A),
> PINMUX_IPSR_GPSR(IP3SR1_19_16, MSIOF4_SYNC),
I think this part belongs in "[PATCH v3 03/21] pinctrl: renesas:
Initial R8A779G0 (V4H) PFC support", as it is a bug in that patch.
>
> /* IP0SR2 */
> @@ -2228,6 +2233,29 @@ static const unsigned int scif3_ctrl_mux[] = {
> RTS3_N_MARK, CTS3_N_MARK,
> };
>
> +/* - SCIF3_A ------------------------------------------------------------------ */
> +static const unsigned int scif3_a_data_pins[] = {
scif3_data_a_pins etc.
> + /* RX3_A, TX3_A */
> + RCAR_GP_PIN(1, 27), RCAR_GP_PIN(1, 28),
> +};
> @@ -2884,6 +2921,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
> SH_PFC_FUNCTION(scif0),
> SH_PFC_FUNCTION(scif1),
> SH_PFC_FUNCTION(scif3),
> + SH_PFC_FUNCTION(scif3_a),
Please drop this, as it is not needed.
> SH_PFC_FUNCTION(scif4),
> SH_PFC_FUNCTION(scif_clk),
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
