[PATCH v3 15/21] pinctrl: renesas: r8a779g0: add missing CANFD5_B

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From: Kuninori Morimoto <kuninori.morimoto.gx@xxxxxxxxxxx>

This patch adds missing CANFD5_B

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@xxxxxxxxxxx>
---
 drivers/pinctrl/renesas/pfc-r8a779g0.c | 21 +++++++++++++++++++--
 1 file changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c
index 68b1c1ba2450..5bee4ab2d132 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
@@ -299,8 +299,8 @@
 #define IP0SR1_31_28	FM(MSIOF0_SS1)		FM(HRX1_X)		FM(RX1_X)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 
 /* IP1SR1 */		/* 0 */			/* 1 */			/* 2 */		/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
-#define IP1SR1_3_0	FM(MSIOF0_SYNC)		FM(HCTS1_X_N)		FM(CTS1_X_N)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR1_7_4	FM(MSIOF0_TXD)		FM(HRTS1_X_N)		FM(RTS1_X_N)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_3_0	FM(MSIOF0_SYNC)		FM(HCTS1_X_N)		FM(CTS1_X_N)	FM(CANFD5_B_TX)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_7_4	FM(MSIOF0_TXD)		FM(HRTS1_X_N)		FM(RTS1_X_N)	FM(CANFD5_B_RX)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1SR1_11_8	FM(MSIOF0_SCK)		FM(HSCK1_X)		FM(SCK1_X)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1SR1_15_12	FM(MSIOF0_RXD)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1SR1_19_16	FM(HTX0)		FM(TX0)			F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -857,10 +857,12 @@ static const u16 pinmux_data[] = {
 	PINMUX_IPSR_GPSR(IP1SR1_3_0,	MSIOF0_SYNC),
 	PINMUX_IPSR_GPSR(IP1SR1_3_0,	HCTS1_X_N),
 	PINMUX_IPSR_GPSR(IP1SR1_3_0,	CTS1_X_N),
+	PINMUX_IPSR_GPSR(IP1SR1_3_0,	CANFD5_B_TX),
 
 	PINMUX_IPSR_GPSR(IP1SR1_7_4,	MSIOF0_TXD),
 	PINMUX_IPSR_GPSR(IP1SR1_7_4,	HRTS1_X_N),
 	PINMUX_IPSR_GPSR(IP1SR1_7_4,	RTS1_X_N),
+	PINMUX_IPSR_GPSR(IP1SR1_7_4,	CANFD5_B_RX),
 
 	PINMUX_IPSR_GPSR(IP1SR1_11_8,	MSIOF0_SCK),
 	PINMUX_IPSR_GPSR(IP1SR1_11_8,	HSCK1_X),
@@ -1498,6 +1500,15 @@ static const unsigned int canfd5_data_mux[] = {
 	CANFD5_TX_MARK, CANFD5_RX_MARK,
 };
 
+/* - CANFD5_B ----------------------------------------------------------------- */
+static const unsigned int canfd5_b_data_pins[] = {
+	/* CANFD5_B_TX, CANFD5_B_RX */
+	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
+};
+static const unsigned int canfd5_b_data_mux[] = {
+	CANFD5_B_TX_MARK, CANFD5_B_RX_MARK,
+};
+
 /* - CANFD6 ----------------------------------------------------------------- */
 static const unsigned int canfd6_data_pins[] = {
 	/* CANFD6_TX, CANFD6_RX */
@@ -2454,6 +2465,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(canfd3_data),
 	SH_PFC_PIN_GROUP(canfd4_data),
 	SH_PFC_PIN_GROUP(canfd5_data),
+	SH_PFC_PIN_GROUP(canfd5_b_data),
 	SH_PFC_PIN_GROUP(canfd6_data),
 	SH_PFC_PIN_GROUP(canfd7_data),
 	SH_PFC_PIN_GROUP(can_clk),
@@ -2650,6 +2662,10 @@ static const char * const canfd5_groups[] = {
 	"canfd5_data",
 };
 
+static const char * const canfd5_b_groups[] = {
+	"canfd5_b_data",
+};
+
 static const char * const canfd6_groups[] = {
 	"canfd6_data",
 };
@@ -2912,6 +2928,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(canfd3),
 	SH_PFC_FUNCTION(canfd4),
 	SH_PFC_FUNCTION(canfd5),
+	SH_PFC_FUNCTION(canfd5_b),
 	SH_PFC_FUNCTION(canfd6),
 	SH_PFC_FUNCTION(canfd7),
 	SH_PFC_FUNCTION(can_clk),
-- 
2.25.1




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