On Thu, May 19, 2022 at 05:31:06PM +0200, Clément Léger wrote:
> Add description of the switch that is present on the RZ/N1 SoC.
>
> Signed-off-by: Clément Léger <clement.leger@xxxxxxxxxxx>
> ---
> arch/arm/boot/dts/r9a06g032.dtsi | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
> index 31c4b2e2950a..20d3dce632ce 100644
> --- a/arch/arm/boot/dts/r9a06g032.dtsi
> +++ b/arch/arm/boot/dts/r9a06g032.dtsi
> @@ -255,6 +255,15 @@ mii_conv5: mii-conv@5 {
> };
> };
>
> + switch: switch@44050000 {
> + compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw";
> + reg = <0x44050000 0x10000>;
> + clocks = <&sysctrl R9A06G032_HCLK_SWITCH>,
> + <&sysctrl R9A06G032_CLK_SWITCH>;
> + clock-names = "hclk", "clk";
> + status = "disabled";
Does the switch port count depend on anything? If it doesn't, maybe you
could add the "ethernet-ports" node and all the ports here, with status
= "disabled", so that board files don't need to spell them out each time?
I'm also thinking you could define the fixed-link and phy-mode = "internal"
property of the CPU port with this occasion. That surely isn't a
per-board thing.
> + };
> +
> gic: interrupt-controller@44101000 {
> compatible = "arm,gic-400", "arm,cortex-a7-gic";
> interrupt-controller;
> --
> 2.36.0
>
