On Wed, May 18, 2022 at 05:58:00AM +0000, Biju Das wrote:
> Hi Rob,
>
> Thanks for the feedback.
>
> > Subject: Re: [RFC 1/8] dt-bindings: soc: renesas: Add RZ/G2L POEG binding
> >
> > On Tue, May 10, 2022 at 04:11:05PM +0100, Biju Das wrote:
> > > Add device tree bindings for the RZ/G2L Port Output Enable for GPT
> > (POEG).
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > > ---
> > > .../soc/renesas/renesas,rzg2l-poeg.yaml | 65 +++++++++++++++++++
> > > 1 file changed, 65 insertions(+)
> > > create mode 100644
> > > Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-poeg.yaml
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-poeg.yam
> > > l
> > > b/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-poeg.yam
> > > l
> > > new file mode 100644
> > > index 000000000000..5737dbf3fa45
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-poeg
> > > +++ .yaml
> > > @@ -0,0 +1,65 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > > +---
> > > +$id:
> "
> > > +
> > > +title: Renesas RZ/G2L Port Output Enable for GPT (POEG)
> > > +
> > > +maintainers:
> > > + - Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > > +
> > > +description:
> >
> > '|' needed.
>
> OK.
>
> >
> > > + The output pins of the general PWM timer (GPT) can be disabled by
> > > + using the port output enabling function for the GPT (POEG).
> > > + Specifically, either of the following ways can be used.
> > > + * Input level detection of the GTETRGA to GTETRGD pins.
> > > + * Output-disable request from the GPT.
> > > + * Register settings.
> > > +
> > > +properties:
> > > + compatible:
> > > + items:
> > > + - enum:
> > > + - renesas,r9a07g044-poeg # RZ/G2{L,LC}
> > > + - renesas,r9a07g054-poeg # RZ/V2L
> > > + - const: renesas,rzg2l-poeg
> > > +
> > > + reg:
> > > + maxItems: 1
> > > +
> > > + interrupts:
> > > + maxItems: 1
> > > +
> > > + clocks:
> > > + maxItems: 1
> > > +
> > > + power-domains:
> > > + maxItems: 1
> > > +
> > > + resets:
> > > + maxItems: 1
> > > +
> > > +required:
> > > + - compatible
> > > + - reg
> > > + - interrupts
> > > + - clocks
> > > + - power-domains
> > > + - resets
> > > +
> > > +additionalProperties: false
> > > +
> > > +examples:
> > > + - |
> > > + #include <dt-bindings/clock/r9a07g044-cpg.h>
> > > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > > +
> > > + poeggd: poeg@10049400 {
> > > + compatible = "renesas,r9a07g044-poeg", "renesas,rzg2l-poeg";
> > > + reg = <0x10049400 0x4>;
> >
> > This looks like it is part of some larger block?
>
> There are 2 IP blocks GPT(PWM) and POEG with its own resources like (register map, clk, reset and interrupts)
>
> Larger block is GPT, which has lot of functionalities. The output from GPT block can be disabled
> by this IP either by external trigger, request from GPT(Deadtime error, both output low/high)
> or explicit software control). This IP has only a single register. Currently I am not sure which framework
> to be used for this IP?? Or should it be merged with larger block GPT by combining the resources?
Usually, IP blocks would have some minimum address alignment (typ 4K or
64K to be page aligned), but if there's no other IP in this address
range as-is is fine. The question is what's before or after the above
address?
Rob
