Re: [PATCH v5 4/5] rtc: rzn1: Add oscillator offset support

[kernel test robot <lkp@xxxxxxxxx>]

Hi Miquel,

I love your patch! Perhaps something to improve:

[auto build test WARNING on abelloni/rtc-next]
[also build test WARNING on robh/for-next linus/master v5.18-rc6]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/intel-lab-lkp/linux/commits/Miquel-Raynal/RZ-N1-RTC-support/20220512-224022
base:   https://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux.git rtc-next
config: mips-allyesconfig (https://download.01.org/0day-ci/archive/20220513/202205130445.mjHjgcBv-lkp@xxxxxxxxx/config)
compiler: mips-linux-gcc (GCC) 11.3.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/intel-lab-lkp/linux/commit/1b2c010278819d2c7aab406d9718a659ead047cf
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Miquel-Raynal/RZ-N1-RTC-support/20220512-224022
        git checkout 1b2c010278819d2c7aab406d9718a659ead047cf
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.3.0 make.cross W=1 O=build_dir ARCH=mips SHELL=/bin/bash drivers/rtc/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@xxxxxxxxx>

All warnings (new ones prefixed by >>):

   drivers/rtc/rtc-rzn1.c: In function 'rzn1_rtc_set_offset':
>> drivers/rtc/rtc-rzn1.c:275:29: warning: variable 'ppb_per_step' set but not used [-Wunused-but-set-variable]
     275 |         unsigned int steps, ppb_per_step;
         |                             ^~~~~~~~~~~~


vim +/ppb_per_step +275 drivers/rtc/rtc-rzn1.c

   271	
   272	static int rzn1_rtc_set_offset(struct device *dev, long offset)
   273	{
   274		struct rzn1_rtc *rtc = dev_get_drvdata(dev);
 > 275		unsigned int steps, ppb_per_step;
   276		int stepsh, stepsl;
   277		u32 val;
   278		int ret;
   279	
   280		/*
   281		 * Check which resolution mode (every 20 or 60s) can be used.
   282		 * Between 2 and 124 clock pulses can be added or substracted.
   283		 *
   284		 * In 20s mode, the minimum resolution is 2 / (32768 * 20) which is
   285		 * close to 3051 ppb. In 60s mode, the resolution is closer to 1017.
   286		 */
   287		stepsh = DIV_ROUND_CLOSEST(offset, 1017);
   288		stepsl = DIV_ROUND_CLOSEST(offset, 3051);
   289	
   290		if (stepsh >= -0x3E && stepsh <= 0x3E) {
   291			ppb_per_step = 1017;
   292			steps = stepsh;
   293			val |= RZN1_RTC_SUBU_DEV;
   294		} else if (stepsl >= -0x3E && stepsl <= 0x3E) {
   295			ppb_per_step = 3051;
   296			steps = stepsl;
   297		} else {
   298			return -ERANGE;
   299		}
   300	
   301		if (!steps)
   302			return 0;
   303	
   304		if (steps > 0) {
   305			val |= steps + 1;
   306		} else {
   307			val |= RZN1_RTC_SUBU_DECR;
   308			val |= (~(-steps - 1)) & 0x3F;
   309		}
   310	
   311		ret = readl_poll_timeout(rtc->base + RZN1_RTC_CTL2, val,
   312					 !(val & RZN1_RTC_CTL2_WUST), 100, 2000000);
   313		if (ret)
   314			return ret;
   315	
   316		writel(val, rtc->base + RZN1_RTC_SUBU);
   317	
   318		return 0;
   319	}
   320	

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