On 5/10/22 12:03 PM, Phil Edworthy wrote: > Document the Ethernet AVB IP found on RZ/V2M SoC. > It includes the Ethernet controller (E-MAC) and Dedicated Direct memory > access controller (DMAC) for transferring transmitted Ethernet frames > to and received Ethernet frames from respective storage areas in the > RAM at high speed. > The AVB-DMAC is compliant with IEEE 802.1BA, IEEE 802.1AS timing and > synchronization protocol, IEEE 802.1Qav real-time transfer, and the > IEEE 802.1Qat stream reservation protocol. > > R-Car has a pair of combined interrupt lines: > ch22 = Line0_DiA | Line1_A | Line2_A > ch23 = Line0_DiB | Line1_B | Line2_B > Line0 for descriptor interrupts (which we call dia and dib). > Line1 for error related interrupts (which we call err_a and err_b). > Line2 for management and gPTP related interrupts (mgmt_a and mgmt_b). > > RZ/V2M hardware has separate interrupt lines for each of these. > > It has 3 clocks; the main AXI clock, the AMBA CHI (Coherent Hub > Interface) clock and a gPTP reference clock. > > Signed-off-by: Phil Edworthy <phil.edworthy@xxxxxxxxxxx> > Reviewed-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> Reviewed-by: Sergey Shtylyov <s.shtylyov@xxxxxx> I'm not an expert in the DT bindings, though... > --- > v3: > - No change > v2: > - Instead of reusing ch22 and ch24 interupt names, use the proper names Interrupt. :-) [...] MBR, Sergey
