Hi Prabhakar,
On Mon, May 9, 2022 at 9:24 PM Lad, Prabhakar
<prabhakar.csengg@xxxxxxxxx> wrote:
> On Mon, May 9, 2022 at 10:10 AM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
> > On Mon, May 9, 2022 at 9:22 AM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> > > > Subject: [PATCH v2 2/5] irqchip: Add RZ/G2L IA55 Interrupt Controller
> > > > driver
> > > >
> > > > Add a driver for the Renesas RZ/G2L Interrupt Controller.
> > > >
> > > > This supports external pins being used as interrupts. It supports one line
> > > > for NMI, 8 external pins and 32 GPIO pins (out of 123) to be used as IRQ
> > > > lines.
> > > >
> > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> >
> > > > --- /dev/null
> > > > +++ b/drivers/irqchip/irq-renesas-rzg2l.c
> >
> > > > +static void rzg2l_irqc_irq_disable(struct irq_data *d) {
> > > > + unsigned int hw_irq = irqd_to_hwirq(d);
> > > > +
> > > > + if (hw_irq >= IRQC_TINT_START && hw_irq <= IRQC_TINT_COUNT) {
> > > > + struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> > > > + u32 offset = hw_irq - IRQC_TINT_START;
> > > > + u32 tssr_offset = TSSR_OFFSET(offset);
> > > > + u8 tssr_index = TSSR_INDEX(offset);
> > > > + u32 reg;
> > > > +
> > > > + raw_spin_lock(&priv->lock);
> > > > + reg = readl_relaxed(priv->base + TSSR(tssr_index));
> > > > + reg &= ~(TSSEL_MASK << tssr_offset);
> > > > + writel_relaxed(reg, priv->base + TSSR(tssr_index));
> > > > + raw_spin_unlock(&priv->lock);
> > > > + }
> > > > + irq_chip_disable_parent(d);
> > > > +}
> >
> > > > +static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type) {
> > > > + struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> > > > + unsigned int hwirq = irqd_to_hwirq(d);
> > > > + u32 titseln = hwirq - IRQC_TINT_START;
> > > > + u32 offset;
> > > > + u8 sense;
> > > > + u32 reg;
> > > > +
> > > > + switch (type & IRQ_TYPE_SENSE_MASK) {
> > > > + case IRQ_TYPE_EDGE_RISING:
> > > > + sense = TITSR_TITSEL_EDGE_RISING;
> > > > + break;
> > > > +
> > > > + case IRQ_TYPE_EDGE_FALLING:
> > > > + sense = TITSR_TITSEL_EDGE_FALLING;
> > > > + break;
> > > > +
> > > > + default:
> > > > + return -EINVAL;
> > > > + }
> > > > +
> > >
> > > > + if (titseln < TITSR0_MAX_INT) {
> > > > + offset = TITSR0;
> > > > + } else {
> > > > + titseln /= TITSEL_WIDTH;
> > > > + offset = TITSR1;
> > > > + }
> > >
> > > as TITSR0 (0x24) and TITSR1(0x28) are contiguous address location
> > >
> > > May be like others, above declare it as
> > > u32 offset = TITSR0; ??
> > >
> > > and here
> > > if ((titseln >= TITSR0_MAX_INT) {
> > > titseln /= TITSEL_WIDTH;
> > > offset += 4;
> > > }
> >
> > Why "titseln /= TITSEL_WIDTH"?
> > Shouldn't that be "titseln -= TITSR0_MAX_INT"?
>
> Ouch, that should be "titseln -= TITSR0_MAX_INT".
>
> > Do I need more coffee?
> >
> > Can't you define TITSR_{OFFSET,INDEX}() helper macros, like for
> > TSSR above?
> >
> you mean a macro to get the TITSELx offset?
Either a macro, or an open-coded calculation (if you need it in only
one place).
As TITSR0 and TITSR1 are stored contiguous, you can easily
derive offset/shift from irq index.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
