Hello!
On 5/4/22 5:54 PM, Phil Edworthy wrote:
> RZ/V2M has a separate gPTP reference clock that is used when the
> AVB-DMAC Mode Register (CCC) gPTP Clock Select (CSEL) bits are
> set to "01: High-speed peripheral bus clock".
> Therefore, add a feature that allows this clock to be used for
> gPTP.
>
> Signed-off-by: Phil Edworthy <phil.edworthy@xxxxxxxxxxx>
> Reviewed-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Reviewed-by: Sergey Shtylyov <s.shtylyov@xxxxxx>
[...]
> diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h
> index 73976a392457..f8706897ea41 100644
> --- a/drivers/net/ethernet/renesas/ravb.h
> +++ b/drivers/net/ethernet/renesas/ravb.h
> @@ -1032,6 +1032,7 @@ struct ravb_hw_info {
> unsigned gptp:1; /* AVB-DMAC has gPTP support */
> unsigned ccc_gac:1; /* AVB-DMAC has gPTP support active in config mode */
> unsigned gptp_ptm_gic:1; /* gPTP enables Presentation Time Match irq via GIC */
> + unsigned gptp_ref_clk:1; /* gPTP has separate reference clock */
Perhaps just gptp_clk?
[...]
> @@ -1043,6 +1044,7 @@ struct ravb_private {
> void __iomem *addr;
> struct clk *clk;
> struct clk *refclk;
I wonder what that refclk feeds -- no word of it in the commit adding it...
> + struct clk *gptp_clk;
> struct mdiobb_ctrl mdiobb;
> u32 num_rx_ring[NUM_RX_QUEUE];
> u32 num_tx_ring[NUM_TX_QUEUE];
[...]
MBR, Sergey
