On Sat, Apr 30, 2022 at 08:59:11AM +0100, Biju Das wrote: > Add device tree bindings for the RZ/G2L General PWM Timer (GPT). > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > --- > .../bindings/pwm/renesas,rzg2l-gpt.yaml | 104 ++++++++++++++++++ > 1 file changed, 104 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml > > diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml > new file mode 100644 > index 000000000000..0e44c0fbe04a > --- /dev/null > +++ b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml > @@ -0,0 +1,104 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pwm/renesas,rzg2l-gpt.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas RZ/G2L General PWM Timer (GPT) > + > +maintainers: > + - Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > + > +properties: > + compatible: > + items: > + - enum: > + - renesas,r9a07g044-gpt # RZ/G2{L,LC} > + - renesas,r9a07g054-gpt # RZ/V2L > + - const: renesas,rzg2l-gpt > + > + reg: > + # base address and length of the registers block for the PWM. Yes, that's all 'reg', drop. > + maxItems: 1 > + > + '#pwm-cells': > + # should be 2. See pwm.yaml in this directory for a description of > + # the cells format. 2 cells the schema says already. The reference for the format is okay, but move it to a 'description' entry. > + const: 2 > + > + interrupts: > + items: > + - description: GTCCRA input capture/compare match > + - description: GTCCRB input capture/compare > + - description: GTCCRC compare match > + - description: GTCCRD compare match > + - description: GTCCRE compare match > + - description: GTCCRF compare match > + - description: GTADTRA compare match > + - description: GTADTRB compare match > + - description: GTCNT overflow/GTPR compare match > + - description: GTCNT underflow > + > + interrupt-names: > + items: > + - const: ccmpa > + - const: ccmpb > + - const: cmpc > + - const: cmpd > + - const: cmpe > + - const: cmpf > + - const: adtrga > + - const: adtrgb > + - const: ovf > + - const: unf > + > + clocks: > + # clock phandle and specifier pair. That's all 'clocks', drop. > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > + resets: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - interrupts > + - interrupt-names > + - clocks > + - power-domains > + - resets > + > +allOf: > + - $ref: pwm.yaml# > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/r9a07g044-cpg.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + gpt4: pwm@10048400 { > + compatible = "renesas,r9a07g044-gpt", "renesas,rzg2l-gpt"; > + reg = <0x10048400 0xa4>; > + interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 272 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 273 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 274 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 275 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 276 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 278 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>; > + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", > + "cmpe", "cmpf", "adtrga", "adtrgb", > + "ovf", "unf"; > + clocks = <&cpg CPG_MOD R9A07G044_GPT_PCLK>; > + power-domains = <&cpg>; > + resets = <&cpg 523 R9A07G044_GPT_RST_C>; > + #pwm-cells = <2>; > + }; > -- > 2.25.1 > >
