Hi Phil,
On Tue, May 3, 2022 at 2:02 PM Phil Edworthy <phil.edworthy@xxxxxxxxxxx> wrote:
> The RZ/V2M doesn't have a matching set of reset monitor regs for each reset
> reg like the RZ/G2L. Instead, it has a single CPG_RST_MON reg which has a
> single bit per module.
>
> Signed-off-by: Phil Edworthy <phil.edworthy@xxxxxxxxxxx>
> Reviewed-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> ---
> v3:
> - If no clk mon regs and no clk monitor bit specified, return an error
Thanks for the update!
> --- a/drivers/clk/renesas/rzg2l-cpg.c
> +++ b/drivers/clk/renesas/rzg2l-cpg.c
> @@ -1177,8 +1177,16 @@ static int rzg2l_cpg_status(struct reset_controller_dev *rcdev,
> const struct rzg2l_cpg_info *info = priv->info;
> unsigned int reg = info->resets[id].off;
> u32 bitmask = BIT(info->resets[id].bit);
> + s8 monbit = info->resets[id].monbit;
>
> - return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
> + if (info->has_clk_mon_regs) {
> + return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
> + } else if (monbit >= 0) {
> + u32 monbitmask = BIT(monbit);
> +
> + return !!(readl(priv->base + CPG_RST_MON) & monbitmask);
> + }
> + return -ENOTSUPP;
I had my doubts about -ENOTSUPP, but
drivers/reset/core.c:reset_control_status() confirms it's the right
error code to return.
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-clk-for-v5.19.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
