On Tue, May 3, 2022 at 2:01 PM Phil Edworthy <phil.edworthy@xxxxxxxxxxx> wrote:
> Define RZ/V2M (R9A09G011) Clock Pulse Generator module clock outputs
> (CPG_CLK_ON* registers), and reset definitions (CPG_RST_* registers)
> in Section 48.5 ("Register Description") of the RZ/V2M Hardware User's
> Manual (Rev. 1.10, Sep. 2021).
>
> Signed-off-by: Phil Edworthy <phil.edworthy@xxxxxxxxxxx>
> Reviewed-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> ---
> v3:
> - Add missing clocks and resets.
> - Change names of ETH clocks to ETH0, even though there is just one ETH,
> to match the HW manual.
> - Change names of IIC PCLKs to better match the HW manual
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in a branch shared by driver and DT source files.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
