On Sat, Apr 30, 2022 at 1:42 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> M3 clock is sourced from DSI Divider (DSIDIVA * DSIDIVB)
>
> This patch add support for DSI divider clk by combining
> DSIDIVA and DSIDIVB.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> ---
> v2->v3:
> * Dropped the blank line abd defined variables in
> reverse Xmas tree order in get_vclk_parent_rate()
> * Added macro MAX_VCLK_FREQ and rate is checked against
> this macro in determine_rate and set_rate
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-clk-for-v5.19, with the rest of this series.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
