Add RSPI{0,1,2} nodes to R9A07G043 (RZ/G2UL) SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 43 +++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 55bf4b72304f..4d17c8814a8d 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -158,11 +158,52 @@ ssi3: ssi@1004a800 { status = "disabled"; }; + spi0: spi@1004ac00 { + compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; + reg = <0 0x1004ac00 0 0x400>; + interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G043_RSPI0_CLKB>; + resets = <&cpg R9A07G043_RSPI0_RST>; + power-domains = <&cpg>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + spi1: spi@1004b000 { + compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; reg = <0 0x1004b000 0 0x400>; + interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G043_RSPI1_CLKB>; + resets = <&cpg R9A07G043_RSPI1_RST>; + power-domains = <&cpg>; + num-cs = <1>; #address-cells = <1>; #size-cells = <0>; - /* place holder */ + status = "disabled"; + }; + + spi2: spi@1004b400 { + compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; + reg = <0 0x1004b400 0 0x400>; + interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G043_RSPI2_CLKB>; + resets = <&cpg R9A07G043_RSPI2_RST>; + power-domains = <&cpg>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; scif0: serial@1004b800 { -- 2.25.1