Hi Biju,
On Wed, Apr 27, 2022 at 11:48 AM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> PLL5 generates FOUTPOSTDIV clk and is sourced by LCDC/DSI modules.
> The FOUTPOSTDIV is connected to PLL5_4 MUX. Video clock is sourced
> from DSI divider which is connected to PLL5_4 MUX.
>
> This patch adds support for generating FOUTPOSTDIV clk.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> ---
> V1->V2:
> * Added Rb tag from Geert
> * Added Code comments related to clk handling
> * Split struct rzg2l_pll5_param and added struct
> rzg2l_pll5_mux_dsi_div_param for priv.
> * Added {get_foutpostdiv_rate, get_vclk_rate} helper function
> * used div_u64 to avoid overflow on 32 bit systems
> * Added CPG_SIPLL5_STBY_DOWNSPREAD_WEN macro
> * Added pl5_spread and updated CPG_SIPLL5_CLK5 setting.
Thanks for the update!
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> --- a/drivers/clk/renesas/rzg2l-cpg.h
> +++ b/drivers/clk/renesas/rzg2l-cpg.h
> @@ -49,6 +65,8 @@
> #define SEL_SDHI0 DDIV_PACK(CPG_PL2SDHI_DSEL, 0, 2)
> #define SEL_SDHI1 DDIV_PACK(CPG_PL2SDHI_DSEL, 4, 2)
>
> +#define EXTAL_FREQ_IN_MEGA_HZ (24)
Ideally, we'd obtain this from DT. But given all RZ/G2L-alike SoCs
support only 24 MHz clock inputs, I guess this is OK.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
