As per the latest RZ/G2L Hardware User's Manual (Rev.1.10 Apr, 2022), the bit 31 of TSU OTP Calibration Register(OTPTSUTRIM) indicates whether bit [11:0] of OTPTSUTRIM is valid or invalid. This patch updates the code to reflect this change. Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> --- drivers/thermal/rzg2l_thermal.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/thermal/rzg2l_thermal.c b/drivers/thermal/rzg2l_thermal.c index 7a9cdc1f37ca..be07e04c6926 100644 --- a/drivers/thermal/rzg2l_thermal.c +++ b/drivers/thermal/rzg2l_thermal.c @@ -32,6 +32,8 @@ #define TSU_SS 0x10 #define OTPTSUTRIM_REG(n) (0x18 + ((n) * 0x4)) +#define OTPTSUTRIM_EN_MASK BIT(31) +#define OTPTSUTRIM_MASK GENMASK(11, 0) /* Sensor Mode Register(TSU_SM) */ #define TSU_SM_EN_TS BIT(0) @@ -183,11 +185,15 @@ static int rzg2l_thermal_probe(struct platform_device *pdev) pm_runtime_get_sync(dev); priv->calib0 = rzg2l_thermal_read(priv, OTPTSUTRIM_REG(0)); - if (!priv->calib0) + if (priv->calib0 & OTPTSUTRIM_EN_MASK) + priv->calib0 &= OTPTSUTRIM_MASK; + else priv->calib0 = SW_CALIB0_VAL; priv->calib1 = rzg2l_thermal_read(priv, OTPTSUTRIM_REG(1)); - if (!priv->calib1) + if (priv->calib1 & OTPTSUTRIM_EN_MASK) + priv->calib1 &= OTPTSUTRIM_MASK; + else priv->calib1 = SW_CALIB1_VAL; platform_set_drvdata(pdev, priv); -- 2.25.1
