Hi Geert, Thanks for the feedback. > Subject: Re: [PATCH v8 5/5] media: renesas: vsp1: Add support for RZ/G2L > VSPD > > Hi Biju, > > On Tue, Apr 19, 2022 at 8:18 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > wrote: > > The RZ/G2L VSPD provides a single VSPD instance. It has the following > > sub modules MAU, CTU, RPF, DPR, LUT, BRS, WPF and LIF. > > > > The VSPD block on RZ/G2L does not have a version register, so added a > > new compatible string "renesas,r9a07g044-vsp2" with a data pointer > > containingthe info structure. Also the reset line is shared with the > > DU module. > > > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> > > Reviewed-by: Kieran Bingham <kieran.bingham+renesas@xxxxxxxxxxxxxxxx> > > --- > > v7->v8: > > * Split the patch for adding s/w version, feature bit and RZ/G2L > > support > > * Added feature bit VSP1_HAS_NON_ZERO_LBA to device_info > > * Added .soc for RZ/G2L > > * Replaced the compatible "renesas,rzg2l-vsp2" -> "renesas,r9a07g044- > vsp2" > > Thanks for the update! > > > --- a/drivers/media/platform/renesas/vsp1/vsp1_regs.h > > +++ b/drivers/media/platform/renesas/vsp1/vsp1_regs.h > > @@ -767,6 +767,8 @@ > > #define VI6_IP_VERSION_MODEL_VSPDL_GEN3 (0x19 << 8) > > #define VI6_IP_VERSION_MODEL_VSPBS_GEN3 (0x1a << 8) > > #define VI6_IP_VERSION_MODEL_VSPD_V3U (0x1c << 8) > > +/* RZ/G2L SoC's have no version register, So use 0x80 as the model > > +version */ > > RZ/G2L SoCs OK. > > > +#define VI6_IP_VERSION_MODEL_VSPD_RZG2L (0x80 << 8) > > > > #define VI6_IP_VERSION_SOC_MASK (0xff << 0) > > #define VI6_IP_VERSION_SOC_H2 (0x01 << 0) > > @@ -780,6 +782,8 @@ > > #define VI6_IP_VERSION_SOC_M3N (0x04 << 0) > > #define VI6_IP_VERSION_SOC_E3 (0x04 << 0) > > #define VI6_IP_VERSION_SOC_V3U (0x05 << 0) > > +/* RZ/G2L SoC have no version register, So use 0x80 for SoC > > +Identification */ > > RZ/G2L SoCs OK, as it is applicable to both RZ/G2L and RZ/G2LC SoCs. Regards, biju > > > +#define VI6_IP_VERSION_SOC_RZG2L (0x80 << 0) > > > > #define VI6_IP_VERSION_VSP_SW (0xfffe << 16) /* SW VSP version > */ >
