Add support for M3 clock which is sourced from DSI divider connected
to PLL5_4 mux.
Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
---
V1->V2:
* No change
RFC->V1:
* Added Rb tag from Geert
---
drivers/clk/renesas/r9a07g044-cpg.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index d350d6dce4b1..cee552bdf3cc 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -56,6 +56,7 @@ enum clk_ids {
CLK_SD1_DIV4,
CLK_SEL_GPU2,
CLK_SEL_PLL5_4,
+ CLK_DSI_DIV,
/* Module Clocks */
MOD_CLK_BASE,
@@ -87,7 +88,7 @@ static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };
static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" };
static const struct {
- struct cpg_core_clk common[50];
+ struct cpg_core_clk common[52];
#ifdef CONFIG_CLK_R9A07G054
struct cpg_core_clk drp[0];
#endif
@@ -166,6 +167,8 @@ static const struct {
DEF_FIXED("M1", R9A07G044_CLK_M1, CLK_PLL5_FOUTPOSTDIV, 1, 1),
DEF_FIXED("M2", R9A07G044_CLK_M2, CLK_PLL3_533, 1, 2),
DEF_FIXED("M2_DIV2", CLK_M2_DIV2, R9A07G044_CLK_M2, 1, 2),
+ DEF_DSI_DIV("DSI_DIV", CLK_DSI_DIV, CLK_SEL_PLL5_4, CLK_SET_RATE_PARENT),
+ DEF_FIXED("M3", R9A07G044_CLK_M3, CLK_DSI_DIV, 1, 1),
},
#ifdef CONFIG_CLK_R9A07G054
.drp = {
--
2.25.1
