Hi Phil,
Thanks for your patch!
On Wed, Mar 30, 2022 at 5:42 PM Phil Edworthy <phil.edworthy@xxxxxxxxxxx> wrote:
> The rz/v2m SoC doesn't use CLK_MON registers, so make it optional.
RZ/V2M ... them
>
> Signed-off-by: Phil Edworthy <phil.edworthy@xxxxxxxxxxx>
> Reviewed-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> drivers/clk/renesas/r9a07g044-cpg.c | 4 ++++
> drivers/clk/renesas/rzg2l-cpg.c | 25 +++++++++++++++----------
> drivers/clk/renesas/rzg2l-cpg.h | 3 +++
> 3 files changed, 22 insertions(+), 10 deletions(-)
This needs an update for the new drivers/clk/renesas/r9a07g043-cpg.c.
> --- a/drivers/clk/renesas/rzg2l-cpg.c
> +++ b/drivers/clk/renesas/rzg2l-cpg.c
> @@ -498,16 +498,18 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
> if (!enable)
> return 0;
>
> - for (i = 1000; i > 0; --i) {
> - if (((readl(priv->base + CLK_MON_R(reg))) & bitmask))
> - break;
> - cpu_relax();
> - }
> + if (priv->info->has_clk_mon_regs) {
> + for (i = 1000; i > 0; --i) {
> + if (((readl(priv->base + CLK_MON_R(reg))) & bitmask))
> + break;
> + cpu_relax();
> + }
>
> - if (!i) {
> - dev_err(dev, "Failed to enable CLK_ON %p\n",
> - priv->base + CLK_ON_R(reg));
> - return -ETIMEDOUT;
> + if (!i) {
> + dev_err(dev, "Failed to enable CLK_ON %p\n",
> + priv->base + CLK_ON_R(reg));
> + return -ETIMEDOUT;
> + }
or just insert:
if (!priv->info->has_clk_mon_regs)
return 0;
and no more changes are needed to this function.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
