Hi Biju,
On Fri, Mar 18, 2022 at 6:51 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> Add PLL5_4 clk mux support to select clock from clock
> sources FOUTPOSTDIV and FOUT1PH0.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> ---
> RFC->V1:
> * Removed LUT.
Thanks for the update!
> --- a/drivers/clk/renesas/rzg2l-cpg.c
> +++ b/drivers/clk/renesas/rzg2l-cpg.c
> @@ -71,6 +71,7 @@ struct rzg2l_pll5_param {
> u8 pl5_intin;
> u8 pl5_postdiv1;
> u8 pl5_postdiv2;
> + u8 clksrc;
> };
I understand you cannot use the plain DEF_MUX() here, as "clksrc"
is set up in pll5_params in the DSI divider (patch 3), and you rely
on parent propagation again to program the mux according to that?
I think it would help to document that somewhere.
The rest LGTM, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
