On Mon, Apr 18, 2022 at 12:02:52PM +0300, Sergey Shtylyov wrote:
> Hello!
>
> On 4/14/22 10:40 AM, Herve Codina wrote:
>
> > Add the device node for the r9a06g032 internal PCI bridge device.
> >
> > Signed-off-by: Herve Codina <herve.codina@xxxxxxxxxxx>
> > ---
> > arch/arm/boot/dts/r9a06g032.dtsi | 28 ++++++++++++++++++++++++++++
> > 1 file changed, 28 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
> > index 636a6ab31c58..848dc034bb8c 100644
> > --- a/arch/arm/boot/dts/r9a06g032.dtsi
> > +++ b/arch/arm/boot/dts/r9a06g032.dtsi
> > @@ -211,6 +211,34 @@ gic: interrupt-controller@44101000 {
> > interrupts =
> > <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
> > };
> > +
> > + pci_usb: pci@40030000 {
> > + compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1";
> > + device_type = "pci";
> > + clocks = <&sysctrl R9A06G032_HCLK_USBH>,
> > + <&sysctrl R9A06G032_HCLK_USBPM>,
> > + <&sysctrl R9A06G032_CLK_PCI_USB>;
> > + clock-names = "hclk_usbh", "hclk_usbpm", "clk_pci_usb";
> > + reg = <0x40030000 0xc00>,
> > + <0x40020000 0x1100>;
> > + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> > + status = "disabled";
> > +
> > + bus-range = <0 0>;
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + #interrupt-cells = <1>;
>
> Really? I don't think this PCI bridge is also an interrupt controller...
'interrupt-map' depends on '#interrupt-cells'.
>
> > + ranges = <0x02000000 0 0x40020000 0x40020000 0 0x00010000>;
> > + /* Should map all possible DDR as inbound ranges, but
> > + * the IP only supports a 256MB, 512MB, or 1GB window.
> > + * flags, PCI addr (64-bit), CPU addr, PCI size (64-bit)
> > + */
> > + dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>;
> > + interrupt-map-mask = <0xf800 0 0 0x7>;
> > + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
> > + 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
> > + 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> > + };
> > };
> >
> > timer {
>
> MBR, Sergey
