On Thu, Apr 14, 2022 at 02:22:41PM +0200, Clément Léger wrote: > This MII converter can be found on the RZ/N1 processor family. The MII > converter ports are declared as subnodes which are then referenced by > users of the PCS driver such as the switch. > > Signed-off-by: Clément Léger <clement.leger@xxxxxxxxxxx> > --- > .../bindings/net/pcs/renesas,rzn1-miic.yaml | 95 +++++++++++++++++++ > include/dt-bindings/net/pcs-rzn1-miic.h | 19 ++++ > 2 files changed, 114 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml > create mode 100644 include/dt-bindings/net/pcs-rzn1-miic.h > > diff --git a/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml b/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml > new file mode 100644 > index 000000000000..ccb25ce6cbde > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml > @@ -0,0 +1,95 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/net/pcs/renesas,rzn1-miic.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas RZ/N1 MII converter > + > +maintainers: > + - Clément Léger <clement.leger@xxxxxxxxxxx> > + > +description: | > + This MII converter is present on the Renesas RZ/N1 SoC family. It is > + responsible to do MII passthrough or convert it to RMII/RGMII. > + > +properties: > + compatible: > + const: renesas,rzn1-miic Need SoC specific compatibles. > + > + reg: > + maxItems: 1 > + > + "#address-cells": > + const: 1 > + > + "#size-cells": > + const: 0 > + > + clocks: > + items: > + - description: MII reference clock > + - description: RGMII reference clock > + - description: RMII reference clock > + - description: AHB clock used for the MII converter register interface > + > + renesas,miic-cfg-mode: > + description: MII mux configuration mode. This value should use one of the > + value defined in dt-bindings/net/pcs-rzn1-miic.h. Describe possible values here as constraints. At present, I don't see the point of this property if there is only 1 possible value and it is required. > + $ref: /schemas/types.yaml#/definitions/uint32 > + > +patternProperties: > + "^mii-conv@[0-4]$": > + type: object additionalProperties: false > + description: MII converter port > + > + properties: > + reg: > + maxItems: 1 Why do you need sub-nodes? They don't have any properties. A simple mask property could tell you which ports are present/active/enabled if that's what you are tracking. Or the SoC specific compatibles you need to add can imply the ports if they are SoC specific. > + > +required: > + - compatible > + - reg > + - clocks > + - renesas,miic-cfg-mode > + - "#address-cells" > + - "#size-cells" > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/net/pcs-rzn1-miic.h> > + #include <dt-bindings/clock/r9a06g032-sysctrl.h> > + > + eth-miic@44030000 { > + compatible = "renesas,rzn1-miic"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x44030000 0x10000>; > + clocks = <&sysctrl R9A06G032_CLK_MII_REF>, > + <&sysctrl R9A06G032_CLK_RGMII_REF>, > + <&sysctrl R9A06G032_CLK_RMII_REF>, > + <&sysctrl R9A06G032_HCLK_SWITCH_RG>; > + renesas,miic-cfg-mode = <MIIC_MUX_MAC2_MAC1_SWD_SWC_SWB_SWA>; > + > + mii_conv0: mii-conv@0 { > + reg = <0>; > + }; > + > + mii_conv1: mii-conv@1 { > + reg = <1>; > + }; > + > + mii_conv2: mii-conv@2 { > + reg = <2>; > + }; > + > + mii_conv3: mii-conv@3 { > + reg = <3>; > + }; > + > + mii_conv4: mii-conv@4 { > + reg = <4>; > + }; > + }; > \ No newline at end of file Fix this. > diff --git a/include/dt-bindings/net/pcs-rzn1-miic.h b/include/dt-bindings/net/pcs-rzn1-miic.h > new file mode 100644 > index 000000000000..c5a0f382967b > --- /dev/null > +++ b/include/dt-bindings/net/pcs-rzn1-miic.h > @@ -0,0 +1,19 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ Dual license please. > +/* > + * Copyright (C) 2022 Schneider-Electric > + * > + * Clément Léger <clement.leger@xxxxxxxxxxx> > + */ > + > +#ifndef _DT_BINDINGS_PCS_RZN1_MIIC > +#define _DT_BINDINGS_PCS_RZN1_MIIC > + > +/* > + * Reefer to the datasheet [1] section 8.2.1, Internal Connection of Ethernet > + * Ports to check the meaning of these values. > + * > + * [1] REN_r01uh0750ej0140-rzn1-introduction_MAT_20210228.pdf > + */ > +#define MIIC_MUX_MAC2_MAC1_SWD_SWC_SWB_SWA 0x13 > + > +#endif > -- > 2.34.1 > >
