On Thu, Apr 14, 2022 at 04:35:46PM +0200, Clément Léger wrote: > > Please keep variable declarations sorted in decreasing order of line > > length (applies throughout the patch series, I won't repeat this comment). > > Acked, both PCS and DSA driver are ok with that rule. Missed that one > though. Are you sure? Because a5psw_port_stp_state_set() says otherwise. > > sizeof(tag), to be consistent with the other use of sizeof() above? > > Although, hmm, I think you could get away with editing "ptag" in place. > > I was not sure of the alignment guarantee I would have here. If the > VLAN header is guaranteed to be aligned on 2 bytes, then I guess it's > ok to do that in-place. If I look at Documentation/core-api/unaligned-memory-access.rst | Alignment vs. Networking | ======================== | | On architectures that require aligned loads, networking requires that the IP | header is aligned on a four-byte boundary to optimise the IP stack. For | regular ethernet hardware, the constant NET_IP_ALIGN is used. On most | architectures this constant has the value 2 because the normal ethernet | header is 14 bytes long, so in order to get proper alignment one needs to | DMA to an address which can be expressed as 4*n + 2. One notable exception | here is powerpc which defines NET_IP_ALIGN to 0 because DMA to unaligned | addresses can be very expensive and dwarf the cost of unaligned loads. Your struct a5psw_tag *ptag starts at 10 bytes (8 for tag, 2 for Ethertype) before the IP header, so I'm thinking it is aligned at a 2 byte boundary as well. A VLAN header between the DSA header and the IP header should also not affect that alignment, since its length is 4 bytes. If "ctrl_tag" is aligned at a 4 byte boundary - 10, it means "ctrl_data" is aligned at a 4 byte boundary - 8, so also a 4 byte boundary. But "ctrl_data2" is aligned at a 4 byte boundary + 2, so you might want to break up the u32 access into 2 u16 accesses, just to be on the safe side?
