Add description of the switch that is present on the RZ/N1 SoC.
Signed-off-by: Clément Léger <clement.leger@xxxxxxxxxxx>
---
arch/arm/boot/dts/r9a06g032.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index 9be55957b8e5..c04b382a20f0 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -250,6 +250,17 @@ mii_conv4: mii-conv@4 {
};
};
+ switch: switch@44050000 {
+ compatible = "renesas,rzn1-a5psw";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x44050000 0x10000>;
+ clocks = <&sysctrl R9A06G032_HCLK_SWITCH>,
+ <&sysctrl R9A06G032_CLK_SWITCH>;
+ clock-names = "hclk_switch", "clk_switch";
+ status = "disabled";
+ };
+
gic: interrupt-controller@44101000 {
compatible = "arm,gic-400", "arm,cortex-a7-gic";
interrupt-controller;
--
2.34.1
