Hi Biju,
On Sat, Apr 2, 2022 at 9:30 AM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> Define RZ/G2UL (R9A07G043U) Clock Pulse Generator Core Clock and module
> clock outputs, as listed in Table 7.1.4.2 ("Clock List r0.51") and also
> add Reset definitions referring to registers CPG_RST_* in Section 7.2.3
> ("Register configuration") of the RZ/G2UL Hardware User's Manual (Rev.
> 0.51, Nov. 2021).
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> Acked-by: Rob Herring <robh@xxxxxxxxxx>
> ---
> v3->v4:
> * Added Ab tag from Rob
> * Removed LAST_COMMON macro from clock and reset indices.
> * Added comment for RZ/G2UL specific clocks
> * Listed all clocks and reset in the same order as RZ/G2L.
Thanks for the update!
> --- /dev/null
> +++ b/include/dt-bindings/clock/r9a07g043-cpg.h
> +/* R9A07G044 Resets */
Oh well...
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in a branch shared by renesas-clk-for-v5.19 and
renesas-arm-dt-for-v5.19, with the above fixed.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
