Add device nodes for the General Purpose Input/Output (GPIO) blocks on
the Renesas R-Car S4-8 (R8A779F0) SoC.
Note that GPIO blocks 4-7 are not added, as they can only be accessed
from the Control Domain.
Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
---
Tested with i2c-gpio, by reading the contents from the I2C EEPROMs
connected to I2C4 (GP1_[89]) on the Spider development board.
Note that this requires manual setting of MOD_SEL1 to zero in U-Boot, as
the pin control driver does not handle this special case yet.
v2:
- Drop gpio4-7],
- Drop RFC,
- Split series in DT bindings+driver series and DTS patch.
---
arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 60 +++++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
index f4e549867371184c..e44b8a44919dc91d 100644
--- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
@@ -75,6 +75,66 @@ pfc: pinctrl@e6050000 {
<0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>;
};
+ gpio0: gpio@e6050180 {
+ compatible = "renesas,gpio-r8a779f0",
+ "renesas,rcar-gen4-gpio";
+ reg = <0 0xe6050180 0 0x54>;
+ interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 915>;
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ resets = <&cpg 915>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pfc 0 0 21>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@e6050980 {
+ compatible = "renesas,gpio-r8a779f0",
+ "renesas,rcar-gen4-gpio";
+ reg = <0 0xe6050980 0 0x54>;
+ interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 915>;
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ resets = <&cpg 915>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pfc 0 32 25>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@e6051180 {
+ compatible = "renesas,gpio-r8a779f0",
+ "renesas,rcar-gen4-gpio";
+ reg = <0 0xe6051180 0 0x54>;
+ interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 915>;
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ resets = <&cpg 915>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pfc 0 64 17>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@e6051980 {
+ compatible = "renesas,gpio-r8a779f0",
+ "renesas,rcar-gen4-gpio";
+ reg = <0 0xe6051980 0 0x54>;
+ interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 915>;
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ resets = <&cpg 915>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pfc 0 96 19>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a779f0-cpg-mssr";
reg = <0 0xe6150000 0 0x4000>;
--
2.25.1
