Add SDHI{0, 1} nodes to RZ/G2UL SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
---
v1->v2:
* Added Rb tag from Geert
---
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 26 ++++++++++++++++++++--
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index ffba6007e3cc..f60186240912 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -334,13 +334,35 @@
};
sdhi0: mmc@11c00000 {
+ compatible = "renesas,sdhi-r9a07g043",
+ "renesas,rcar-gen3-sdhi";
reg = <0x0 0x11c00000 0 0x10000>;
- /* place holder */
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>,
+ <&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>,
+ <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>,
+ <&cpg CPG_MOD R9A07G043_SDHI0_ACLK>;
+ clock-names = "core", "clkh", "cd", "aclk";
+ resets = <&cpg R9A07G043_SDHI0_IXRST>;
+ power-domains = <&cpg>;
+ status = "disabled";
};
sdhi1: mmc@11c10000 {
+ compatible = "renesas,sdhi-r9a07g043",
+ "renesas,rcar-gen3-sdhi";
reg = <0x0 0x11c10000 0 0x10000>;
- /* place holder */
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK>,
+ <&cpg CPG_MOD R9A07G043_SDHI1_CLK_HS>,
+ <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>,
+ <&cpg CPG_MOD R9A07G043_SDHI1_ACLK>;
+ clock-names = "core", "clkh", "cd", "aclk";
+ resets = <&cpg R9A07G043_SDHI1_IXRST>;
+ power-domains = <&cpg>;
+ status = "disabled";
};
phyrst: usbphy-ctrl@11c40000 {
--
2.17.1
