Hi Biju,
On Tue, Mar 15, 2022 at 4:27 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> RZ/G2UL SoC has fewer pins compared to RZ/G2L and the port pin
> definitions are different compared to RZ/G2L.
>
> This patch adds a new compatible to take care of this differences
> by adding r9a07g043_data with r9a07g043_gpio_configs and
> rzg2l_dedicated_pins.common.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Thanks for your patch!
> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> + { "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0,
> + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
> + { "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1,
> + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
> + { "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2,
> + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
> + { "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3,
> + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
> + { "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4,
> + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
> + { "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5,
> + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
> + { "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0,
> + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
> + { "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1,
> + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
> + { "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
While the datasheet states QSPI_INT# has the VMC capability, it does
not state that pin has the Slew Rate capability.
Moreover, the QSPI_INT# functionality is not documented anywhere
else in the datasheet (except for a (stale?) reference in the Boot
Mode chapter), nor in the pinfunction spreadsheet. Hence it looks
like that pin does not exist on RZ/G2UL, and thus should be moved to
rzg2l_pins below.
> + { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) },
> + { "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) },
> + { "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) },
> + { "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) },
> + { "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) },
> + },
> + .rzg2l_pins = {
> + { "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0,
> + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
> + { "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1,
> + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
> + { "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2,
> + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
> + { "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3,
> + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
> + { "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4,
> + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
> + { "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5,
> + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
> + }
> };
The rest LGTM, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
