Hi Biju,
On Tue, Mar 15, 2022 at 3:27 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> The clock structure for RZ/G2UL is almost identical to RZ/G2L SoC with
> fewer IP blocks. The IP blocks such as WDT1, GPT, H264, GPU and POEG are
> not present on RZ/G2UL.
>
> This patch adds minimal clock and reset entries required to boot the
> system on Renesas RZ/G2UL SMARC EVK and binds it with the RZ/G2L CPG core
> driver.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> ---
> v2->v3:
> * Replaced R9A07G043U->R9A07G043 and r9a07g043u->r9a07g043
Thanks for the update!
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> --- /dev/null
> +++ b/drivers/clk/renesas/r9a07g043-cpg.c
> +const struct rzg2l_cpg_info r9a07g043_cpg_info = {
> + /* Core Clocks */
> + .core_clks = r9a07g043_core_clks,
> + .num_core_clks = ARRAY_SIZE(r9a07g043_core_clks),
> + .last_dt_core_clk = LAST_DT_CORE_CLK,
> + .num_total_core_clks = MOD_CLK_BASE,
> +
> + /* Critical Module Clocks */
> + .crit_mod_clks = r9a07g043_crit_mod_clks,
> + .num_crit_mod_clks = ARRAY_SIZE(r9a07g043_crit_mod_clks),
This may need an update if you change the Clock and Reset Definitions.
> +
> + /* Module Clocks */
> + .mod_clks = r9a07g043_mod_clks,
> + .num_mod_clks = ARRAY_SIZE(r9a07g043_mod_clks),
> + .num_hw_mod_clks = R9A07G043_LCDC_CLK_D + 1,
> +
> + /* Resets */
> + .resets = r9a07g043_resets,
> + .num_resets = R9A07G043_LCDC_RESET_N + 1, /* Last reset ID + 1 */
Likewise.
> +};
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
