From: Phil Edworthy <phil.edworthy@xxxxxxxxxxx>
Renesas RZ/N1 SoC features a slightly modified DW UART.
On this SoC, the CPR register value is known but not synthetized in
hardware. We hence need to provide a CPR value in the platform
data. This version of the controller also relies on acting as flow
controller when using DMA, so we need to provide the
'IS_DMA_FLOW_CONTROLLER' quirk.
Signed-off-by: Phil Edworthy <phil.edworthy@xxxxxxxxxxx>
Co-developed-by: Miquel Raynal <miquel.raynal@xxxxxxxxxxx>
Signed-off-by: Miquel Raynal <miquel.raynal@xxxxxxxxxxx>
---
drivers/tty/serial/8250/8250_dw.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
index af9fcc77ee76..efc5c686dbfa 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -758,6 +758,11 @@ static const struct dw8250_platform_data dw8250_armada_38x_data = {
.quirks = DW_UART_QUIRK_ARMADA_38X,
};
+static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {
+ .quirks = DW_UART_QUIRK_IS_DMA_FLOW_CONTROLLER,
+ .cpr = 0x00012f32,
+};
+
static const struct dw8250_platform_data dw8250_starfive_jh7100_data = {
.quirks = DW_UART_QUIRK_SKIP_SET_RATE,
};
@@ -766,7 +771,7 @@ static const struct of_device_id dw8250_of_match[] = {
{ .compatible = "snps,dw-apb-uart" },
{ .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },
{ .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data },
- { .compatible = "renesas,rzn1-uart" },
+ { .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data },
{ .compatible = "starfive,jh7100-hsuart", .data = &dw8250_starfive_jh7100_data },
{ .compatible = "starfive,jh7100-uart", .data = &dw8250_starfive_jh7100_data },
{ /* Sentinel */ }
--
2.27.0
