On Tue, 15 Mar 2022 14:26:40 +0000, Biju Das wrote:
> Define RZ/G2UL (R9A07G043U) Clock Pulse Generator Core Clock and module
> clock outputs, as listed in Table 7.1.4.2 ("Clock List r0.51") and also
> add Reset definitions referring to registers CPG_RST_* in Section 7.2.3
> ("Register configuration") of the RZ/G2UL Hardware User's Manual (Rev.
> 0.51, Nov. 2021).
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> ---
> v2->v3:
> * Removed leading u/U from r9a07g043
> * renamed the file r9a07g043u-cpg.h->r9a07g043-cpg.h
> * Prepared Common Module Clock/Reset indices for RZ/G2UL and RZ/Five
> * Prepared RZ/G2UL specific Module Clock/Reset indices.
> v1->v2:
> * No change
> ---
> include/dt-bindings/clock/r9a07g043-cpg.h | 190 ++++++++++++++++++++++
> 1 file changed, 190 insertions(+)
> create mode 100644 include/dt-bindings/clock/r9a07g043-cpg.h
>
Acked-by: Rob Herring <robh@xxxxxxxxxx>
