On 23/03/2022 15:29, Geert Uytterhoeven wrote:
> Hi Krzysztof,
>
> On Wed, Mar 23, 2022 at 11:44 AM Krzysztof Kozlowski <krzk@xxxxxxxxxx> wrote:
>> On 21/03/2022 16:42, Phil Edworthy wrote:
>>> Define RZ/V2M (R9A09G011) Clock Pulse Generator core clocks, module clock
>>> outputs (CPG_CLK_ON* registers), and reset definitions (CPG_RST_*
>>> registers) in Section 48.5 ("Register Description") of the RZ/V2M Hardware
>>> User's Manual (Rev. 1.10, Sep. 2021).
>>>
>>> Signed-off-by: Phil Edworthy <phil.edworthy@xxxxxxxxxxx>
>>> Reviewed-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
>
>>> --- /dev/null
>>> +++ b/include/dt-bindings/clock/r9a09g011-cpg.h
>>> @@ -0,0 +1,337 @@
>>> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> + *
>>> + * Copyright (C) 2022 Renesas Electronics Corp.
>>> + */
>>> +#ifndef __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__
>>> +#define __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__
>>> +
>>> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
>>
>> Include only headers which you use here. Do you use it directly here?
>
> Technically, it is part of the clock bindings for the SoC.
> That's why it's included here, and in several other *-cpg-mssr.h files.
>
> So I prefer to keep it that way.
Sure, thanks for the explanation. It sill makes header decoupling more
difficult if ever needed, but it's ok.
Acked-by: Krzysztof Kozlowski <krzk@xxxxxxxxxx>
Best regards,
Krzysztof
