Hi Geert,
Thanks for the feedback.
> Subject: Re: [RFC 04/28] clk: renesas: r9a07g044: Add M1 clock support
>
> Hi Biju,
>
> On Wed, Jan 12, 2022 at 6:46 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> wrote:
> > Add support for M1 clock which is sourced from FOUTPOSTDIV.
> >
> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
>
> Thanks for your patch!
>
> > --- a/drivers/clk/renesas/r9a07g044-cpg.c
> > +++ b/drivers/clk/renesas/r9a07g044-cpg.c
>
> The above looks correct to me, so
> Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
>
> > @@ -353,4 +362,7 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info = {
> > /* Resets */
> > .resets = r9a07g044_resets,
> > .num_resets = ARRAY_SIZE(r9a07g044_resets),
> > +
> > + /* lcdc mode for PLL5 settings*/
> > + .pll5_lcdc_dsi_mode = true,
> > };
>
> This is the part I don't like, but I guess you could imagine ;-)
Agreed, Will remove this.
Cheers,
Biju
