[PATCH 0/4] Add GPIO,ETHERNET and SDHI Clock/Reset entries for RZ/G2UL

[Biju Das <biju.das.jz@xxxxxxxxxxxxxx>]

This patch series aims to add GPIO, ETHERNET and SDHI Clock/Reset
entries to RZ/G2UL Clk driver.

This patch series depend upon [1]
[1] https://lore.kernel.org/linux-renesas-soc/20220315142644.17660-6-biju.das.jz@xxxxxxxxxxxxxx/T/#u

Biju Das (4):
  clk: renesas: r9a07g043: Add GPIO clock and reset entries
  clk: renesas: r9a07g043: Add ethernet clock sources
  clk: renesas: r9a07g043: Add GbEthernet clock/reset
  clk: renesas: r9a07g043: Add SDHI clock and reset entries

 drivers/clk/renesas/r9a07g043-cpg.c | 63 +++++++++++++++++++++++++++++
 1 file changed, 63 insertions(+)

-- 
2.17.1