From: Marek Vasut <marek.vasut+renesas@xxxxxxxxx>
This patch adds ZG clocks used by the PowerVR GPU.
Signed-off-by: Marek Vasut <marek.vasut+renesas@xxxxxxxxx>
Cc: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Cc: Niklas Söderlund <niklas.soderlund+renesas@xxxxxxxxxxxx>
Cc: Wolfram Sang <wsa@xxxxxxxxxxxxx>
Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
Cc: linux-renesas-soc@xxxxxxxxxxxxxxx
---
drivers/clk/renesas/r8a7796-cpg-mssr.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 7950313611ef..06257e48b67c 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -85,6 +85,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
/* Core Clock Outputs */
DEF_GEN3_Z("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
+ DEF_GEN3_Z("zg", R8A7796_CLK_ZG, CLK_TYPE_GEN3_Z, CLK_PLL4, 2, 0),
DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@@ -131,6 +132,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
};
static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = {
+ DEF_MOD("3dge", 112, R8A7796_CLK_ZG),
DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1),
DEF_MOD("tmu4", 121, R8A7796_CLK_S0D6),
DEF_MOD("tmu3", 122, R8A7796_CLK_S3D2),
--
2.35.1
