Hi Geert,
On Mon, Mar 14, 2022 at 10:01:14AM +0100, Geert Uytterhoeven wrote:
> On Mon, Mar 14, 2022 at 9:44 AM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> > > On Sat, Mar 12, 2022 at 08:42:03AM +0000, Biju Das wrote:
> > > > Document VSPD found in RZ/G2L and RZ/V2L family SoC's. VSPD block is
> > > > similar to VSP2-D found on R-Car SoC's, but it does not have a version
> > > > register and it has 3 clocks compared to 1 clock on vsp1 and vsp2.
> > > >
> > > > This patch introduces a new compatible 'renesas,rzg2l-vsp2' to handle
> > > > these differences.
> > > >
> > > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
>
> > > > index 990e9c1dbc43..2696a4582251 100644
> > > > --- a/Documentation/devicetree/bindings/media/renesas,vsp1.yaml
> > > > +++ b/Documentation/devicetree/bindings/media/renesas,vsp1.yaml
>
> > > > + clock-names:
> > > > + items:
> > > > + - const: du.0
> > >
> > > Similarly, I'm not sure this is a good name from the point of view of the
> > > VSP.
> >
> > OK, will use the name 'aclk', which is Main clock for this module which is
> > shared with LCDC. 'du.0' is not valid any more here as we are using different
> > CRTC implementation for RZ/G2LC.
> >
> > > > + - const: pclk
> > > > + - const: vclk
> > >
> > > I couldn't find those names in the documentation, where do they come from
> >
> > HW manual (page 312) mentions about LCDC_CLK_A, LCDC_CLK_P & LCDC_CLK_D.
> >
> > Detailed description is mentioned in Clock list document. Please see below.
> >
> > LCDC_CLK_A M0φ PLL3 200 200 LCDC Main clock
> > LCDC_CLK_P ZTφ PLL3 100 100 LCDC Register Access Clock
> > LCDC_CLK_D M3φ SEL_PLL5_4 148.5~5.803 LCDC Video Clock
> >
> > > ? Could you maybe share a DT integration example ?
> >
> > Please see below,
>
> >
> > + du: display@0x10890000 {
> > + compatible = "renesas,du-r9a07g044l";
> > + reg = <0 0x10890000 0 0x10000>;
> > + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
> > + <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
> > + <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
> > + clock-names = "du.0", "pclk", "vclk";
> > + power-domains = <&cpg>;
> > + resets = <&cpg R9A07G044_LCDC_RESET_N>;
> > + reset-names = "du.0";
> > + renesas,vsps = <&vspd0 0>;
>
> Given the DU driver is no longer shared, perhaps all occurrencies of "du"
> should be replaced by "lcdc"?
The LCDC is the combination of the FCPVD, the VSPD and the DU. The first
two are similar to the eponymous IP cores used on R-Car Gen3, while the
DU is a different beast, despite sharing the same name.
--
Regards,
Laurent Pinchart
